The bit extraction process is an important part of algorithms employed by many streaming data applications, including audio, video and communications applications. In order to extract data from a formatted bit stream, the extraction process first has to parse frame headers and sub-headers of the bit stream to determine the size and type of the encoded data. The width of the fields in the header can vary based on previously parsed fields. This makes the bit extraction process time consuming, so that the process typically uses a large percentage of algorithm cycles of a microprocessor, including those based on a RISC (Reduced Instruction Set Computer) with a load/store architecture. The load/store architecture requires that portions of the bit stream are first read from microprocessor memory into one or more registers, which are then used to extract the appropriate bits.
The bit extraction process performed by most conventional microprocessors on formatted streaming data is inherently inefficient given the variability in the field widths within the header of each packet including optional variable-sized packet sub-headers. In particular, in order to extract a variable number of bits from the top of a register, the bit extraction process of conventional configurations required several instructions to shift, generate the mask, keep track of how many bits have been extracted, re-shift and so on. For example, in the digital audio compression standard AC-3, after the computation (mainly FFT, or Fast Fourier Transform) is fully optimized, the bit extraction procedures typically consumed as much as 30-40% of the remaining time. Similarly, when performing Huffman decoding, such as during JPEG (compression standard by the Joint Photographic Experts Group) processing, the bit extraction process typically consumed as much as 40-50% of the total time. Some microprocessors employing a two-instruction method require that interrupts be disabled between the two instructions. Such method inherently decreases efficiency by requiring disablement and re-enablement of interrupts and potentially compromises interrupt-driven processes.
It is desired to provide a microprocessor which extract bits from a bit stream more efficiently to improve performance, including improving performance of applications employing formatted streaming data with variable field widths.